Single-Slope Look-Ahead Ramp ADC
OTT case 08-022 | U.S. Patent 8,724,001
Digital cameras either contain charge-coupled devices (CCDs) or complementary metal-oxide-semiconductor (CMOS) image sensor devices that convert visual images into electric signals. Over the years, designers of CMOS image sensor devices have been moving away from incorporating stand-alone pipeline analog to digital converters (ADC) into these devices to integrating single-slope ADCs that are configured in-line with the pixel array with an ADC for each column of the array. The obvious benefit to this configuration is the ability to move data off the image sensor at a faster speed by processing the columns in parallel. With such a parallel configuration, another less obvious benefit is that performance of each individual ADC can be optimized, allowing for longer settling times, lower noise and higher accuracy. The net result is a camera with a greater shutter speed without compromising image quality.
Researchers at the University of Idaho have developed a technology that further advances the speed of the column-parallel concept for CMOS image sensors by using a device they call a single-slope look-ahead ramp (SSLAR) ADC. The SSLAR-ADC introduces code hopping, fall-back and look-ahead operations considering statistical distribution of the sampled row of information on column sample and hold circuits. This SSLAR-ADC provides between 1.7x and 3.5x ADC speed improvement over current technology, all with less than 1.0% image quality degradation. A result of this shortened ADC conversion time is reduced power consumption and an increased frame rate of the column-parallel CMOS image sensor. This technology would have great utility for cell phone cameras, where minimizing power consumption is more important than a visually imperceptible degradation in image quality.