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Phone: (208) 885-6592
Toll-free: 88-88-UIDAHO
Fax: (208) 885-9052
Email: csinfo@uidaho.edu

Janssen Engineering (JEB)
Room 236

875 Perimeter Drive MS 1010
Moscow, ID 83844-1010

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Contact Debbie Caudle
Phone: (208) 282-7983
Fax: (208) 282-7929
Email: debrac@uidaho.edu

1776 Science Center Drive, Suite 306
Idaho Falls, Idaho 83402

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eo.uidaho.edu

Paul Mawhirter Thesis Defense

Performance Analysis of a Custom Reconfigurable Processor on Space Borne Applications

Tuesday 12:30, April 27, 2010 in the Janssen Engineering Building, room 326.
Major Professor: Dr. Robert Rinker
Abstract:

The purpose of this thesis is to analyze the custom reconfigurable platform Field Programmable Processor Array (FPPA) as compared to traditional space borne general purpose processors (GPP) such as the RAD750 and Coldfire core 2, and other reconfigurable architectures such as the Field Programmable Gate Array (FPGA).

The two associated hypothesis are: The FPPA will perform more efficiently than other choices for spaceborne applications. The FPPA will reconfigure faster than an FPGA implementation. These two hypothesis state that the FPPA will be more efficient than general purpose processors (GPP) and faster than reconfigurable platforms such as the FPGA, as well as quicker reconfiguration time than the FPGA.

The first two parts of the first hypothesis will be supported in the first two experiments GPP vs FPPA and FPGA vs FPPA. The second hypothesis will also be supported in the second experiment. Besides the hypothesis it will be proven that the 16 bit architecture of the FPPA through the use of SIFOpt optimized fixed point real number representation will be a competitive representation to the more expensive hardware implementation of Floating Point Units (FPU).