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Vishal Saxena, Ph.D.

Vishal Saxena, Ph.D.

Associate Professor, Micron Endowed Professor in Microelectronics

Office

Buchanan 318

Phone

208-885-6870

Mailing Address

Electrical and Computer Engineering
University of Idaho
875 Perimeter Drive, MS 1023
Moscow, ID 83844-1023

  • Ph.D., Electrical and Computer Engineering, Boise State University, 2010
  • M.S., Electrical and Computer Engineering, Boise State University, 2007
  • B.Tech., Electrical Engineering, Indian Institute of Technology Madras, 2002

  • Analog and Mixed-Signal Integrated Circuits
    • CMOS Photonic integrated circuits for energy-efficient Terabit/s rate on-chip, chip-to-chip, and data center optical interconnects.
    • Hybrid Mixed-Signal Photonic architectures and Compact Modeling to Harness Light to Transform
    • IC Design.
    • CMOS-based RF and mmWave Photonic architectures, phased-arrays and free-space links.
    • Clock Data Recovery and timing circuits (CDR/PLL) for high-speed interconnects.
    • High-speed Analog-to-digital converters: Continuous-Time Delta-Sigma and RF-to-digital conversion architectures.
  • Neuromorphic Computing
    • High-density Neural-inspired computing ICs with hybrid CMOS and nano-scale emerging devices.
    • Heterogeneous cognitive computing architectures for ultra-low-power deep learning.

Vishal Saxena received a bachelor's in electrical engineering from the Indian Institute of Technology Madras, India in 2002, and the master's and doctorate in electrical and computer engineering from Boise State University, in 2007 and 2010 respectively. From 2010 to Spring 2016, he was with the Electrical and Computer Engineering Department at Boise State University as an assistant and then tenured associate professor. He joined the ECE department at the University of Idaho in fall 2016 as the new Micron Endowed Professor in Microelectronics. His research interests include analog and mixed-signal integrated circuit (IC) design for post-Moore’s scaling era, and harnessing light to transform IC design. These include high-speed hybrid electronic-photonic ICs for next-generation data centers and Cloud infrastructure, integrated RF and mmWave photonic circuits, ultra-low-power neuromorphic deep learning ICs using nano-scale memory devices. Saxena is a member of IEEE, Eta Kappa Nu and Tau Beta Phi. He is a recipient of 2015 National Science Foundation (NSF) CAREER Award, and 2016 Air Force Office of Sponsored Research (AFOSR) Young Investigator (YIP) award. He was selected for the 2016 Idaho’s accomplished under 40 recognition, and his work has been mentioned in the MIT Technology Review. He has served as an associate editor for the IEEE Transactions on Circuits and Systems-II: Express Briefs. He is currently serving on the steering committee of the IEEE International Midwest Symposium on Circuits and Systems, and served in the Boise section of the IEEE Solid-State Circuits Society chapter as its inaugural chair.

  • X. Wu, V. Saxena, and K. Zhu, “A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning,” IEEE Transactions on Circuits and Systems (TCAS) II: Express Briefs, vo. 62. No. 2, pp. 1088-1092, 2015.
  • X. Wu, V. Saxena, and K. Zhu, “Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 254 – 266, June 2015.
  • K. Zhu, V. Saxena, X. Wu, and W. Kuang, “Design Considerations for Traveling-Wave Modulator Based CMOS Photonic Transmitters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 4, pp. 412 – 416, April 2015.
  • Z. Kehan, V. Saxena, and X. Wu, “A Comprehensive Design Approach for a MZM Based PAM-4 Silicon Photonic Transmitter,” in proc. International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, USA, Aug 2015.
  • K. Zhu, V. Saxena and W. Kuang, “Compact Verilog-A Modeling of Silicon Traveling-Wave Modulator for Hybrid CMOS Photonic Circuit Design,” in proc. 57th IEEE International. Midwest Symposium on Circuits and Systems, College Station, Aug. 3-6, 2014.

  • NSF CAREER Award: Mixed-Signal Photonics Interconnects for Energy-Efficient High-Performance Data Interfaces, (PI:Saxena), $500,000, 2015 – 2020.
  • AFOSR, Young Investigator Program (YIP) Award: Realizing Large-scale Integrated RF Photonic Signal Processing Systems, (PI:Saxena), $360,000, 2016 – 2019.

  • 2016 Idaho’s Accomplished under 40 (AU40) Award from Idaho Business Review 
  • 2016 AFOSR Young Investigator Award
  • 2015 NSF CAREER Award
  • 2013 Best Student Paper Award co-author for "Systematic Design of 10-bit 50MS/s Pipelined ADC," in IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED) 2013, Boise, Idaho
  • 2012 Finalist co-author for the Best Student Paper Award in the 55th Midwest Symposium on Circuits and Systems (MWSCAS) 2012, Boise
  • 2011 Finalist co-author for the Best Student Paper Award in the 54th Midwest Symposium on Circuits and Systems (MWSCAS) 2011, Seoul, South Korea
  • 2009 Finalist author for the Best Student Paper Award in the 52nd Midwest Symposium on Circuits and Systems (MWSCAS) 2009, Cancun, Mexico
  • 2006 Best Student Paper Award for "Indirect Feedback Compensation of CMOS Opamps," in IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED) 2006, Boise, Idaho

Contact Us

Buchanan Engineering Building Rm. 213

Mailing Address:

Electrical and Computer Engineering
University of Idaho
875 Perimeter Drive MS 1023
Moscow, ID 83844-1023

Phone: 208-885-6554

Fax: 208-885-7579

Email: info@ece.uidaho.edu