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Suat Ay, Ph.D.


Office: Gauss-Johnson Lab 212
Phone: 208-885-2783
Email: suatay@uidaho.edu
Mailing Address: Department of Electrical and Computer Engineering
P.O. Box 441023
Moscow, Idaho 83844-1023

College of Engineering
Electrical and Computer Engineering Department
Assistant Professor

Campus Locations: Moscow
With UI Since 2007


  • Research/Focus Areas
    • Mixed-signal VLSI design
    • analog electronics
    • image sensors
  • Biography

    Dr. Suat U. Ay is an assistant professor of electrical and computer engineering at the University of Idaho. He received his master's and doctoral degrees in electrical engineering-electrophysics from the University of Southern California (USC), Los Angeles, in 1997 and 2005. From September 1997 to July 2005, he worked in the industry as VLSI Design Engineer specializing in the area of mixed-signal analog design of CMOS image sensors. He was with Photobit Corporation which later became the Micron Technology Inc.’s Imaging Division in 2001. He joined the Department of Electrical and Computer Engineering at the University of Idaho in 2007.

    His research focuses on the application of analog and mixed-signal circuit design techniques on micro-nano technologies to a new class of baseband/RF circuits and systems; intelligent sensor systems with an emphasis on the reconfigurable, secure, flexible electro-optical circuit and devices; and smart CMOS image sensors. He also leads the VLSI Sensors Research Group (VSRG).

    He is a member of IEEE Solid State Circuits, IEEE Circuit and Systems, IEEE Electron Devices and SPIE societies.

  • Selected Publications

    [1] Suat Utku Ay , Large Format CMOS Image Sensors: Performance and Design, VDMVerlag Dr. Muller Press, 2008 (ISBN:978-3-8364-7052-0) [Buy]

    [2]  Jose Mumbru, Krishna V. Shenoy, George Panotopoulos, Suat Ay, Xin An, Fai Mok and Demetri Psaltis "Reconfigurable Processors for Neural Prostheses", pp.335-368 Published in "Toward Replacement Parts for the Brain: Implantable Biomimetic Electronics as Neural Prostheses" Edited by Theodore W. Berger and Dennis L. Glanzman, MIT Press, June 2005 (ISBN 0-262-02577-9)

     

    1] S. Balagopal, S. U. Ay, “An On-chip Ramp Generator for Single-Slope Look Ahead Ramp (SSLAR) ADC,” IEEE 2009 Midwest Symposium on Circuits and Systems (MWSCAS), August 2-5, 2009, Cancun, Mexico (in press)

     
    [2]
    S. U. Ay, “A Nanowatt Cascadable Delay Element for Compact Power-on-Reset (POR) Circuits,” IEEE 2009 Midwest Symposium on Circuits and Systems (MWSCAS) August 2-5, 2009, Cancun, Mexico (in press)

     
    [3]
    F.Z. Nelson, M.N. Alam, S.U.Ay,” A Single-Slope Look-Ahead Ramp (SSLAR) ADC for Column Parallel CMOS Image Sensors,“ 2009 IEEE Workshop on Microelectronics and Electron Devices, pp.77-80, Boise, ID, April 3, 2009

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