## Department of Electrical & Computer Engineering

### Moscow

Buchanan Engineering Building Rm. 213

Electrical and Computer Engineering
University of Idaho
875 Perimeter Drive MS 1023
Moscow, ID 83844-1023

Phone: 208-885-6554

Fax: 208-885-7579

Email: info@ece.uidaho.edu

# Saied Hemati, Ph.D.

## Assistant Professor

Office

Buchanan 316

Phone

208-885-6504

Email

c/o Department of Electrical and Computer Engineering
PO Box 441023
Moscow, Idaho 83844-1023

• Ph.D., Carleton University, 2005
• M.S., Isfahan University of Technology, 1997
• B.S., Isfahan University of Technology, 1993

### Research/Focus Areas

• Novel Integrated Circuit Design for Communications Systems
• IoT and Cyber-Physical Systems
• Hardware Cybersecurity in Communication Systems
• Information Theory and Channel Coding Applications
• Low-Power/High-Speed Analog/Digital Integrated Circuit Design

### Biography

Saied Hemati received the bachelor's and master's degrees in electronics engineering from Isfahan University of Technology, in 1993 and 1997, respectively, and the doctorate in electrical engineering from Carleton University, in 2005.

From 1997 to 1999, he worked at the Integrated Electronics Industry (IEI) in Isfahan, Iran. From 1999 to 2001, he was a researcher at the Research and Education Center of Isfahan Telecommunication Company. From 2005 to 2007, he was an NSERC postdoctoral fellow and a part-time professor at the School of Information Technology and Engineering at the University of Ottawa. He was an assistant professor at the Department of Electrical Engineering at Sharif University of Technology, in 2008. He was with the Department of Electrical and Computer Engineering at McGill University, as a senior researcher and lecturer from 2008 to 2012. Then he was an associate professor with the Electrical Engineering Department at Linkoping University in Sweden, and he joined the Department of Electrical and Computer Engineering at the University of Idaho, Moscow, in August 2013. His research interests include the theory of operation and the design and implementation of iterative error-correcting decoders.

Hemati is the recipient of several awards and scholarships, including the Senate Medal for outstanding academic achievement, a ReSMiQ postdoctoral fellowship, an NSERC (Natural Sciences and Engineering Research Council of Canada) postdoctoral fellowship, a CSA (Canadian Space Agency) NSERC postdoctoral supplement award, a CITO (Communications and Information Technology Ontario) research excellence award, an Ontario Graduate Scholarship, an Ontario Graduate Scholarship in Science and Technology, and the best paper award in the CITO Knowledge Network Conference in 2002.

### Publications

#### Journal Publications

• S. Hemati, F. Leduc-Primeau, and W. Gross, "A Relaxed Min-Sum LDPC Decoder with Simplified Check Node Operation," IEEE Communications Letters, vol. 20, no. 3, pp. 422-425, March 2016.
• K. Cushon, S. Hemati, C. Leroux, S. Mannor, and W. J. Gross, "High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing," IEEE Transactions on Signal Processing. vol. 62, no. 3, pp.619- 631, February 2014.
• A. Ciobanu, S. Hemati, and W. J. Gross, "Adaptive Multiset Stochastic Decoding of Non-binary LDPC Codes," IEEE Transactions on Signal Processing, vol. 61, no. 16, pp.4100-4113, August 2013.
• F. Leduc-Primeau, S. Hemati, S. Mannor, and W. J. Gross, "Relaxed Half-Stochastic Belief Propagation," IEEE Transactions on Communications, vol. 61, no. 5, pp. 1648- 1659, May 2013.
• G. Sarkis, S. Hemati, S. Mannor, and W. J. Gross, "Stochastic Decoding of LDPC Codes over GF(q)," IEEE Transactions on Communications, vol. 61, no. 3, pp. 939- 950, March 2013.
• F. Leduc-Primeau, S. Hemati, S. Mannor, and W. J. Gross, "Dithered Belief Propagation Decoding," IEEE Transactions on Communications, vol. 60, no. 8, pp. 2042-2047, August 2012.
• G. He, G. Sarkis, S. Hemati, W. J. Gross, and B. Bai "Low-Complexity Channel Likelihood Estimation for Non-Binary Codes and High-Order Modulations," IEEE Communications Letters, vol. 16, no. 6, pp. 801-804, June 2012.
• K. Cushon, C. Leroux, S. Hemati, S. Mannor, and W. J. Gross, "A Min-Sum Iterative Decoder with Pulse Width Message Encoding," IEEE Transactions on Circuits and Systems-II, vol. 58, no. 11, pp. 893-897, November 2010.
• C. Leroux, S. Hemati, S. Mannor, and W. J. Gross, "Stochastic Chase Decoding of Reed-Solomon Codes," IEEE Communications Letters, vol. 14, no. 9, pp. 863-865, September 2010.
• S. Sharifi Tehrani, A. Naderi, G.-A. Kamendje, S. Hemati, S. Mannor, and W. J. Gross "Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding," IEEE Transactions on Signal Processing, vol. 58, no. 9, pp. 4883-4896, September 2010.
• S. Hemati and A. Yongacoglu, "On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach," IEEE Transactions on Communications, vol. 58, no. 8, pp. 2225-2231, August 2010.
• S. Hemati and A. Yongacoglu, "Dynamics of Analog Decoders for Different Message Representation Domains," IEEE Transactions on Communications, vol. 58, no. 3, pp. 721-723, March 2010.
• N. Mobini, A. H. Banihashemi, and S. Hemati, "A Differential Binary Message-Passing LDPC Decoder," IEEE Transactions on Communications, vol. 57, no. 9, pp. 2518-2523, September 2009.
• S. Hemati and A. H. Banihashemi, "Convergence Speed and Throughput of Analog Decoders," IEEE Transactions on Communications, vol. 55, no.5, pp. 833-836, May 2007.
• S. Hemati, A. H. Banihashemi, and C. Plett, "A 0.18 $\mu$m Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2531-2540, Nov. 2006.
• S. Hemati and A. H. Banihashemi, "Dynamics and Performance Analysis of Analog Iterative Decoding for Low-Density Parity-Check (LDPC) Codes," IEEE Transactions on Communications, vol. 54, no.1, pp. 61-70, Jan. 2006.
• M. R. Yazdani, S. Hemati, and A. H. Banihashemi, "Improving Belief Propagation on Graphs with Cycles," IEEE Communications Letters, vol. 8, no. 1, pp. 57-59, Jan. 2004.
• S. Feiz and S. Hemati, "Dispersion Evaluation in Optical Waveguides," Esteghlal, J. of Engineering, vol. 18, no.1, pp. 23-31, 1999.

#### Conference Presentations

• A. B. Z. Sadeque and S. Hemati, “High Speed, Low Power, and Accurate Analogto-Digital Data Converters (ADCs) For Medical Implant Devices Applications,” Technical Research Exhibition (TRE) in NSBE Region VI Fall Regional Conference (FRC), November 2015, Riverside, California. Awarded the 2nd best award.
• A. B. Z. Sadeque and S. Hemati, “A 5-bit Pulse width Modulation Based ADC in 130 nm Technology For Ultra Low Power Applications,” Technical Research Exhibition (TRE) in 41st NSBE National Convention, March 2015, Anaheim, California.
• A. Wang, S. Hemati, and W. Gross, “Efficient Implementation of Structured Long Block-Length LDPC Codes,” Accepted for presentation at the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, IEEE ASAP 2015, Toronto, Canada, July 2015.
• K. Cushon, S. Hemati, S. Mannor, and W. Gross, “Energy-Efficient Gear-Shift LDPC Decoders,” in Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, IEEE ASAP 2014, IBM Research - Zurich, Switzerland, June 18-20, 2014.
• R. H´eloir, C. Leroux, S. Hemati, M. Arzel, and W. Gross, “Stochastic Chase Decoder for Reed-Solomon Codes,” in Proceedings of the 10-th IEEE NEWCAS Conference, pp. 1-6, Montreal, Canada, 2012.
• F. Leduc-Primeau, S. Hemati, W. Gross, and S. Mannor, “Lowering Error Floors Using Dithered Belief Propagation,” in Proceedings of the IEEE Globecom 2010 Communication Theory Symposium, pp. 1-6, Miami, FL, USA.
• G. Sarkis, S. Hemati, W. Gross, and S. Mannor, “Relaxed Half-Stochastic Decoding of LDPC Codes over GF(q),” in Proceedings of Annual Allerton Conference on Communication, Control and Computing , pp. 36-41, University of Illinois, 2010.
• F. Leduc-Primeau, S. Hemati, W. Gross, and S. Mannor, “A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes,” in Proceedings of IEEE Globecom 2009 Communication Theory Symposium, pp. 1-6, Nov. 2009, Honolulu, Hawaii, USA.
• S. Hemati and A. Yongacoglu, “On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach,” in Proceedings of CWIT 2009, Ottawa, Canada, pp. 29-31, May 13-15, 2009.
• S. Hemati and A. Yongacoglu, “Effects of Message Representation Domain on the Dynamics of Analog Decoders,” in Proceedings of the 2008 Analog Decoding Workshop, Utah, US, July 2008.
• N. Mobini, A. H. Banihashemi, and S. Hemati, “A Differential Binary MessagePassing LDPC Decoder,” in Proceedings of the IEEE Globecom 2007 Communication Theory Symposium, Washington, DC, US, pp. 1561-1565, Nov. 2007.
• S. Hemati and A. Yongacoglu, “On the Dynamics of Analog Min-Sum Iterative Decoders, an Analytical Approach,” in Proceedings of the 2007 IEEE International Symposium on Information Theory, ISIT2007, Nice, France, June, 2007.
• S. Hemati and A. Yongacoglu, “Stability and Singularity in Analog Min-Sum Decoders,” in Proceedings of the 6th Analog Decoding Workshop, Montreal, Canada, May 2007.
• N. Mobini, A. H. Banihashemi, and S. Hemati, “Differential Decoding of LDPC Codes with Binary Message-Passing,” in Proceedings of the 6th Analog Decoding Workshop, Montreal, Canada, May 2007.
• S. Hemati and A. Yongacoglu, “On the Solvability of the Dynamic Equations for Analog Min-Sum Decoders,” in Proceedings of the 5th Analog Decoding Workshop, Turin, Italy, pp. 47-50, June 2006.
• S. Hemati and A. H. Banihashemi, “Convergence Speed and Throughput of Analog Iterative Decoders for Low-Density Parity-Check (LDPC) Codes,” in Proceedings of the 4th International Symposium on Turbo Codes, Munich, Germany, April 3 - 7, 2006.
• S. Hemati and A. H. Banihashemi, “A Low-Voltage 4-Input CMOS Analog Maximum Winner-Take-All Chip for Min-Sum Analog Iterative Decoders,” The CMC Microsystems 2006 Annual Symposium, Ottawa, October 2006.
• S. Hemati and A. H. Banihashemi, “Convergence Speed and Throughput of Analog Decoders,” in Proceedings of CWIT 2005, Montreal, Quebec, Canada, pp. 235-238, June 5 - 8, 2005.
• S. Hemati, A. H. Banihashemi, and C. Plett, “An 80-Mb/s 0.18-µm CMOS Analog Min-Sum Iterative Decoder for a (32,8,10) LDPC Code,” in Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Jose, California, pp. 240-243, Sept. 18 -21, 2005.
• S. Hemati, A. H. Banihashemi, and C. Plett, “A High-Speed Analog Min-Sum Iterative Decoder,” in Proceedings of the IEEE International Symposium on Information Theory, ISIT 2005, Adelaide, Australia, pp. 1768-1772, Sept. 4 - 9, 2005.
• S. Hemati, A. H. Banihashemi, and C. Plett, and N. Ogbebor “An Analog MinSum Decoder for a (32,8) LDPC Code,” in Proceedings of CWIT 2005, Montreal, Quebec, Canada, pp. 203-206, June 5 - 8, 2005.
• S. Hemati and A. H. Banihashemi, “A Novel CMOS Analog Min-Sum Iterative Decoder,” Microsystems Research and Development in Canada 2004, Ottawa, Canada, Sept. 2004.
• S. Hemati and A.H. Banihashemi, “Comparison between Continuous-Time Asynchronous and Discrete-Time Synchronous Iterative Decoding,” in Proceedings of the IEEE Globecom 2004, Dallas, Texas, USA, pp. 356-360, Nov. 29 - Dec. 3, 2004.
• S. Hemati and A.H. Banihashemi, “On the Dynamics of Continuous-Time Analog Iterative Decoders,” in Proceedings of the 2004 IEEE International Symposium on Information Theory, ISIT2004, Chicago, US, p. 262, June 27-July 2, 2004.
• S. Hemati and A. H. Banihashemi, “A Current-Mode Maximum Winner-Take-All Circuit with Low Voltage Requirement for Min-Sum Analog Iterative Decoders,” in Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003, Sharjah, UAE, pp. 5-7, December 14 -17, 2003.
• S. Hemati and A. H. Banihashemi, “Novel Circuits for Implementing High-Degree Parity-Check and Variable Nodes in Full CMOS Analog Min-Sum Iterative Decoders,” 2nd Analog Decoding Workshop, Zurich, Switzerland, September 2003.
• S. Hemati and A. H. Banihashemi, “Full CMOS Min-Sum Analog Iterative Decoder,” in Proceedings of the 2003 IEEE International Symposium on Information Theory, ISIT2003, Yokohama, Japan , p. 347, June 29-July 4, 2003.
• S. Hemati and A. H. Banihashemi, “Iterative Decoding in Analog CMOS,” in Proceedings of the 13th ACM Great Lakes Symposium on VLSI, ACM GLSVLSI 2003, Washington D.C., USA, pp. 15-20, April 27-29, 2003.
• S. Hemati and A. H. Banihashemi, “On the Dynamics of Analog Asynchronous Iterative Decoders,” in Proceedings of the 41st Annual Allerton Conference on Communication, Control and Computing , University of Illinois, US, pp. 1679-1687, October 1-3, 2003.
• S. Hemati and A. H. Banihashemi, “Analog Asynchronous Iterative Decoding, Different Dynamics with Better Performance,” 2nd Analog Decoding Workshop, Zurich, Switzerland, September 2003.
• M. R. Yazdani, S. Hemati, and A. H. Banihashemi, “Improving Belief Propagation on Graphs with Cycles,” in Proceedings of the 2003 Canadian Conference on Information Theory, CWIT2003, Waterloo, Ontario, Canada, pp. 235-238, May 18-21, 2003.
• S. Hemati and M. Emadi, “A Method for Analyzing Higher-Order Dispersion in Optical Fiber,” in Proceedings of the 2003 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2003, Montreal, Canada, pp. 289-292, May 4-7, 2003.
• F. Farahmand and S. Hemati, “An Algorithm Based on Evolutionary Programming for Training Artificial Neural Networks with Non-Conventional Neurons,” in Proceedings of the 2003 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2003, Montreal, Canada, pp. 1845-1848, May 4 -7, 2003.
• S. Hemati and A. H. Banihashemi, “Low-Cost High-Performance Analog Iterative Decoders,” 2002 Cito Knowledge Network Conference, Ottawa, Canada, Oct. 2002. Awarded the best paper award
• S. Hemati and A. H. Banihashemi, “Advanced Coding Schemes in Modern WDM Networks,” 2002 Cito Knowledge Network Conference, Ottawa, Canada, Oct. 2002.
• A. H. Banihashemi and S. Hemati, “Decoding in Optics,” in Proceedings of the 2002 IEEE International Symposium on Information Theory, ISIT 2002, Lausanne, Switzerland, p. 231, June 30-July 5, 2002.
• S. Hemati and A. H. Banihashemi, “New Analog VLSI Circuits for Iterative Decoding,” in Proceedings of the 21st Biennial Symposium on Communications, Queen’s University, Kingston, Ontario, Canada, pp. 261-263, June 2-5, 2002.
• A. H. Banihashemi and S. Hemati, “ Electro-optical Implementation of Iterative Decoding Algorithms,” in Proceedings of the 21st Biennial Symposium on Communications, Queen’s University, Kingston, Ontario, Canada., pp. 474-475, June 2-5, 2002.
• S. Hemati and A. H. Banihashemi, “Towards Photonic Decoders,” in Technical digest of the Eighth Microptics Conference, MOC’01, Osaka, Japan, pp. 218-221, October 2001.
• S. Hemati,“ WDM Optical Components”, Eighth Iranian Conference on Electrical Engineering, ICEE2000, Isfahan University of Technology, Isfahan, Iran, May 2000.
• A. Adibi, V. Tahani, S. Hemati, and F. Farahmand, “ Neural Networks with NonConventional Synapses,” in Proceedings of the Eighth Iranian Conference on Electrical Engineering, ICEE2000, Isfahan, Iran, pp. 68-75, May 2000.
• A. Adibi and S. Hemati, “A Novel Implementation of the Hebbian Neurons by Subthreshold MOSFETs in the Presence of Mobile Ions, ” in Proceedings of the Seventh Iranian Conference on Electrical Engineering, ICEE99, Iran Telecommunication Research Center, Tehran, Iran, pp. 41-48, May 1999.
• S. Feiz and S. Hemati, “ Precise Formula for Zero Material Dispersion Analysis of the Optical Fiber Core,” in Proceedings of the International Conference on Communication, Computer, and Power, ICCCP98, Sultan Qaboos University, Muscat, Sultanate of Oman, pp. 19-23, December 1998.
• S. Feiz and S. Hemati, “Dispersion Evaluation by Monte Carlo Simulation,” in Proceedings of the Fifth Iranian Physics Conference, Optics Session, Iran University of Science and Technology, Tehran, Iran, pp. 11-14, June 1998. Awarded the Gold Medal by Iran Electronics Industry
• S. Feiz, S. Hemati, and M. Bahadoran,“ Evaluation of Material Dispersion in Optical Fibers According to Instantaneous Spectrum of the Light Source,” in Proceedings of the sixth Iranian Conference on Electrical Engineering, ICEE98, K.N. Toosi University of Technology, Tehran, Iran, pp. 79-84, May 1998.
• S. Feiz, S. Hemati, and M. Emadi, “ Exact Determination of Material Dispersion in SI Optical Fibers,” in Proceedings of the Fifth Iranian Conference on Electrical Engineering, ICEE97, Sharif University of Technology, Tehran, Iran, pp. 24-31, May 1997.
• S. Feiz and S. Hemati, “ Exact Determination of the Derivatives of the Refractive Index of the Optical Fiber Core,” in Proceedings of the Fourth Iranian Conference on Electrical Engineering, ICEE96, University of Tehran, Tehran, Iran, pp. 225-228, May 1996.

#### Books

• Saied Hemati, Iterative Decoding in Analog VLSI, Dynamics and Circuits, VDM Verlag, ISBN: 978-3-639-17539-4, 2009.

### Awards and Honors

• ReSMiQ Fellowship, September 2009 ($20,000) • Promoted to IEEE Senior Member, March 2008 • Canadian Space Agency NSERC Postdoctoral Fellowship Supplement Award, April 2006 ($26,666)
• The Senate Medal for Outstanding Academic Achievements, November 2005
• Prestigious NSERC Postdoctoral Fellowship in Integrated Circuit Design, March 2005 ($80,000) • Ontario Graduate Scholarship (OGS), April 2004 ($15,000)
• Ontario Graduate Scholarship in Science and Technology (OGSST), September 2003 ($10,000) • CITO Research Excellence Scholarship, May 2003 ($5,000)
• Best Poster Award, 2002 CITO Knowledge Network Conference, Ottawa, Canada, Oct. 2002 ($500) • CITO Graduate Scholarship, 2002 ($2,000)
• Carleton University Graduate Scholarship, 2001-2005
• Integrated Electronics Industry Golden Medal Paper Award, 1998
• Ranked 35 in the Iranian National University Entrance Exam (Graduate-Level) in Electrical Engineering among over 20,000 contestants in 1993
• Ranked 77 in the Iranian National University Entrance Exam among over 100,000 contestants in 1988

### U.S. Patents

• Hemati and S. Rahmani, “Method and System for Transferring Signals and Materials between Inside and Outside Body Through Oral Cavity”, US patent (pending), US 14/739,556 Filing date June 16, 2014.
• W. Gross, F. Leduc-Primeau, S. Hemati, and S. Mannor, “A Method and System for Decoding” US patent No: 8,898,537; issued on Nov. 25, 2014.
• A. H. Banihashemi and S. Hemati, “Full CMOS Min-Sum Analog Iterative Decoders” US Patent No: 7,769,798; issued on August 3, 2010.

### Moscow

Buchanan Engineering Building Rm. 213